Digital control implementations for voltage regulators have a digital PWM (pulse width modulator) that generates a duty cycle pulse from an input digital word. Traditionally this DPWM (digital pulse width modulator) involves a delay line and a counter to achieve the best compromise for area and power. It also involves some asynchronous logic to create the PWM (pulse width modulation) pulse and the presence of asynchronous logic would mean a lot more verification and validation to ensure that the PWM pulses are monotonic and uniformly varying with the input digital word. However, traditional schemes are not catered to extend to high frequency applications (e.g., 100 MHz or higher) where the resolutions for the time quantization are less than a single buffer of a given process node.